[vc_row el_class=”inner-body-content” css=”.vc_custom_1666779388840{padding-top: 30px !important;padding-bottom: 20px !important;}”][vc_column][vc_custom_heading text=”Pre-requisite(s)” font_container=”tag:h2|font_size:20px|text_align:left” use_theme_fonts=”yes” css=”.vc_custom_1666779363570{margin-top: 0px !important;}”][vc_column_text]Computer Organization and Assembly Language (CS-2523)

Introduction to Programming (CS-1133)[/vc_column_text][vc_custom_heading text=”Recommended Book(s)” font_container=”tag:h2|font_size:20px|text_align:left” use_theme_fonts=”yes”][vc_column_text]Computer Architecture: A Quantitative Approach, 5^th Edition John L. Hennessy And David A. Patterson. Morgan Kaufmann Publishers[/vc_column_text][vc_custom_heading text=”COURSE OBJECTIVES” use_theme_fonts=”yes”][vc_column_text]

[/vc_column_text][vc_custom_heading text=”COURSE LEARNING OUTCOMES (CLO)” font_container=”tag:h3|text_align:left” use_theme_fonts=”yes”][vc_column_text]Course Objectives[/vc_column_text][vc_custom_heading text=”COURSE CONTENTS” use_theme_fonts=”yes”][vc_custom_heading text=”Quantitative Principles of Computer Design ” font_container=”tag:h3|text_align:left” use_theme_fonts=”yes”][vc_column_text]The Task of a Computer Designer
Technology and Computer Usage Trends
Cost and Trends in Cost
Measuring and Reporting Performance
Benchmarks and metrics[/vc_column_text][vc_custom_heading text=”Instruction Set Principles and Examples ” font_container=”tag:h3|text_align:left” use_theme_fonts=”yes”][vc_column_text]Classification of Instruction Set Architectures
Instruction Formats and Semantics
Memory Addressing Modes
Operations in the Instruction Set
Encoding and Instruction Set
The Role of Compilers[/vc_column_text][vc_custom_heading text=”Advanced Pipelining and Instruction-Level Parallelism” font_container=”tag:h3|text_align:left” use_theme_fonts=”yes”][vc_column_text]Basic Pipeline Operations
Data and Control Pipeline Hazards
Instruction-Level Parallelism
Dynamic Instruction Scheduling and Branch Prediction[/vc_column_text][vc_custom_heading text=”Thread Level Parallelism ” font_container=”tag:h3|text_align:left” use_theme_fonts=”yes”][vc_column_text]Multiprocessor Systems and Applications
Centralized Shared-Memory Architectures
Distributed Shared-Memory Architectures
Execution Synchronization
Models of Memory Consistency[/vc_column_text][vc_custom_heading text=”Data Level Parallelism (Time Permitting)” font_container=”tag:h3|text_align:left” use_theme_fonts=”yes”][vc_column_text]Vector Processing
Support for Multimedia Applications
Graphics Processing Units[/vc_column_text][vc_custom_heading text=”MAPPING OF CLOs TO ASSESSMENT MODULES” font_container=”tag:h2|font_size:20px|text_align:left” use_theme_fonts=”yes”][vc_column_text css=”.vc_custom_1666779350869{margin-bottom: 0px !important;}”]

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