[vc_row el_class=”inner-body-content” css=”.vc_custom_1666778032789{padding-top: 30px !important;padding-bottom: 20px !important;}”][vc_column][vc_custom_heading text=”Pre-requisite(s)” font_container=”tag:h2|font_size:20px|text_align:left” use_theme_fonts=”yes” css=”.vc_custom_1666778014309{margin-top: 0px !important;}”][vc_column_text]None[/vc_column_text][vc_custom_heading text=”Recommended Book(s)” font_container=”tag:h2|font_size:20px|text_align:left” use_theme_fonts=”yes”][vc_column_text]Logic And Computer Design Fundamentals, By M. Morris Mano & Charles R Kime. 2nd Edition, Prentice Hall Inc.[/vc_column_text][vc_custom_heading text=”Reference Book(s)” font_container=”tag:h2|font_size:20px|text_align:left” use_theme_fonts=”yes”][vc_column_text]Digital Fundamentals Tenth Edition, 2009, Thomas L. Floyd, Pearson[/vc_column_text][vc_custom_heading text=”COURSE OBJECTIVES” use_theme_fonts=”yes”][vc_column_text]To introduce the concepts and tools for the design of digital electronic circuits.[/vc_column_text][vc_custom_heading text=”COURSE LEARNING OUTCOMES (CLO)” font_container=”tag:h3|text_align:left” use_theme_fonts=”yes”][vc_column_text]Course Objectives[/vc_column_text][vc_custom_heading text=”COURSE CONTENTS” use_theme_fonts=”yes”][vc_custom_heading text=”Number Systems” font_container=”tag:h3|text_align:left” use_theme_fonts=”yes”][vc_column_text]
- Decimal, Binary, Octal, Hexadecimal
- Conversions
- Arithmetic Operations
[/vc_column_text][vc_custom_heading text=”Boolean Algebra & Logic Gates” font_container=”tag:h3|text_align:left” use_theme_fonts=”yes”][vc_column_text]
- Digital logic gates
- Boolean Postulates
- Boolean Functions and their Complements
- Sum of MinTerms
- Product of MaxTerms
- Standard forms
[/vc_column_text][vc_custom_heading text=”Gate level Minimization” font_container=”tag:h3|text_align:left” use_theme_fonts=”yes”][vc_column_text]
- Karnaugh Maps
- Two Variable Maps
- Three Variable Maps
- Four Variable Maps
- Don’t care conditions
- Digital Circuits using Gates
Digital Circuits using NAND gates
[/vc_column_text][vc_custom_heading text=”Combinational Logic” font_container=”tag:h3|text_align:left” use_theme_fonts=”yes”][vc_column_text]
- Analysis and Design
- Code Converters
- Half Adder, Full Adder
- Multiplier
- Decoders and Encoders
- Multiplexers
[/vc_column_text][vc_custom_heading text=”Sequential Circuits” font_container=”tag:h3|text_align:left” use_theme_fonts=”yes”][vc_column_text]
- Latches (SR Latch, D Latch)
- Flip Flops ( D Flip Flop, JK Flip Flop, T Flip Flop)
- Characteristic Tables, Characteristic Equations.
- Analysis of Clocked Sequential Circuits (State Equations, State Tables, State Diagrams)
[/vc_column_text][vc_custom_heading text=”Registers & Counters” font_container=”tag:h3|text_align:left” use_theme_fonts=”yes”][vc_column_text]
- Simple registers
- Registers with parallel Load
- Shift Registers/Serial to parallel Converters
- Universal Shift Register
- Asynchronous/ Synchronous Counter
- Ripple Counters
- Binary Counter
- BCD Counter
- Up-Down Binary Counter
[/vc_column_text][vc_custom_heading text=”Memory and Programmable Logic” font_container=”tag:h3|text_align:left” use_theme_fonts=”yes”][vc_column_text]
- RAM
- ROM
- PLA
- PAL
[/vc_column_text][vc_custom_heading text=”MAPPING OF CLOs TO ASSESSMENT MODULES” font_container=”tag:h2|font_size:20px|text_align:left” use_theme_fonts=”yes”][vc_column_text css=”.vc_custom_1666778001556{margin-bottom: 0px !important;}”]
| Final Exam |
| Assignments |
| Surprise Tests/Quizzes |
| Project |
| Midterm Exam |
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